512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Descriptions
Table 3:
VFBGA Ball Descriptions (Continued)
90-Ball VFBGA
R8, N7, R9, N8,
P9, M8, M7, L8,
L2, M3, M2, P1,
N2, R1, N3, R2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
B1, D2, D3, E2
B2, B7, C9, D9,
E1, L1, M9, N9,
P2, P7
B8, B3, C1, D1,
E9, L9, M1, N1,
P3, P8
A7, F9, L7, R7
A3, F1, L3, R3
E3, E7, K3
–
K2
Symbol
DQ0–DQ31
Type
I/O
Description
Data input/output: Data bus.
54-Ball VFBGA
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
A7, B3, C7, D3
V
DD
Q
Supply DQ power: Provide isolated power to DQ for improved noise
immunity.
Supply DQ ground: Provide isolated ground to DQ for improved noise
immunity.
Supply Core power supply.
Supply Ground.
–
Internally not connected: These balls could be left unconnected,
but it is recommended they be connected to Vss.
–
This TEST pin must be tied to V
SS
or V
SS
Q in normal operation.
–
Should not be used in the application. However, it may be
connected to Vss (ground).
A3, B7, C3, D7
VssQ
A9, E7, J9
A1, E3, J1
–
E2
–
V
DD
V
SS
NC
V
SS
Q
DNU
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
11
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©2005 Micron Technology, Inc. All rights reserved.
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