512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Tru t h Ta b le s
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on
page 24).
9. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
10. Burst in bank n continues as initiated.
11. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with the
data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank will interrupt the WRITE on bank n when registered. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m burst.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
t
t
appearing CL later. The PRECHARGE to bank n will begin after WR is met, where WR
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to
t
t
bank n will begin after WR is met, where WR begins when the WRITE to bank m is regis-
tered. The last valid WRITE to bank n will be data registered one clock to the WRITE to
bank m.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
45
©2005 Micron Technology, Inc. All rights reserved.
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