512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 43:
CLK
tCKS
CKE
tCMS
COMMAND
tCMH
NOP
READ
NOP3
NOP3
PRECHARGE
NOP
ACTIVE
NOP
Single READ – Without Auto Precharge
T0
tCK
tCKH
T1
tCL
tCH
T2
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS
DQM
tAS
ADDR
tAS
A10
tAS
BA0, BA1
tAH
ROW
tCMH
COLUMN
m
ROW
tAH
ROW
ALL BANKS
ROW
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK(S)
BANK
tAH
BANK
tAC
DQ
tRCD
tRAS
tRC
CL
tLZ
tOH
D
OUT
m
tHZ
tRP
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
60
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©2005 Micron Technology, Inc. All rights reserved.
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