512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Re g ist e r De fin it io n
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks or segments of a bank in PASR will be refreshed during self
refresh. It is important to note that data in unused banks or portions of banks will be lost
when PASR is used.
Drive r St re n g t h
Bits E5 and E6 of the extended mode register can be used to select the driver strength of
the DQ outputs. This value should be set according to the application’s requirements.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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