512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Timing Diagrams
Figure 36:
Initialize and Load Mode Register
T0
CLK
((
))
((
))
T1
((
))
((
))
Tn + 1
((
))
((
))
To + 1
((
))
((
))
Tp + 1
((
))
((
))
Tq + 1
((
))
((
))
Tr + 1
((
))
((
))
t
CK
t
CKS
t
CKH
CKE
((
))
((
))
((
))
((
))
((
))
((
))
t
CMS
t
CMH
NOP
PRE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
COMMAND
1
AR
AR
LMR
LMR
VALID
DQM
tAS tAH
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
CODE
VALID
t
AS
tAH
t
AS
t
AH
BA0 = L,
BA1 = L
BA0 = L,
BA0 = L,
BA1 = H
BA1 = L
VALID
BA0, BA1
DQ
((
))
High-Z
((
))
t
RP
((
))
t
RFC
2
((
))
t
RFC
2
((
))
t
MRD
3
((
))
t
MRD
3
((
))
T = 100µs
Power-up:
V
DD
and
CLK
stable
Precharge
all
banks
Load Mode
Register
Load Extended
Mode Register
DON’T
CARE
Notes:
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER
command.
2. Only NOPs or COMMAND INHIBITs may be issued during
t
RFC time.
3. At least one NOP or COMMAND INHIBIT is required during
t
MRD time.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
53
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©2005 Micron Technology, Inc. All rights reserved.
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