512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Notes
Table 16:
Parameter
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
Capacitance (x16)
Note: 2; notes appear on pages 51–52
Symbol
C
I1
C
I2
C
IO
Min
2.0
2.0
2.5
Max
5.0
5.0
6.0
Units
pF
pF
pF
Table 17:
Parameter
Capacitance (x32)
Note: 2; notes appear on pages 51–52
Symbol
C
I1
C
I2
C
IO
Min
2.0
2.0
2.5
Max
5.0
5.0
6.0
Units
pF
pF
pF
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
Notes
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
, V
DD
Q = +1.8V; T
A
= 25°C; ball under test biased at
0.9V, 1.25V, and 1.4V, respectively; f = 1 MHz.
3.
I
DD
is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (–40°C
≤
T
A
≤
+85°C for T
A
on IT parts) is
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (V
DD
and V
DD
Q must be pow-
ered up simultaneously. V
SS
and V
SS
Q must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the
t
REF refresh require-
ment is exceeded.
7. AC characteristics assume
t
T = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
10.
t
HZ defines the time at which the output achieves the open circuit condition; it is not
a reference to V
OH
or V
OL
. The last valid data element will meet
t
OH before going
High-Z.
11. AC timing and I
DD
tests have V
IL
and V
IH
, with timing referenced to V
IH
/2 = crossover
point. If the input transition time is longer than
t
T (MAX), then the timing is refer-
enced at V
IL
(MAX) and V
IH
(MIN) and no longer at the V
IH
/2 crossover point.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
