256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Functional Block Diagrams
The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAM offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
Functional Block Diagrams
Figure 2:
16 Meg x 16 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BA1
0
0
1
1
BA0
0
1
0
1
Bank
0
1
2
3
COMMAND
DECODE
Bank3
Bank2
Bank1
EXT MODE
REGISTER
MODE REGISTER
REFRESH 13
COUNTER
ROW-
ADDRESS
MUX
BANK0
ROW-
ADDRESS
8,192
LATCH
&
DECODER
13
15
13
BANK0
MEMORY
ARRAY
(8,192 x 512 x 16)
2
2
UDQM,
LDQM
Sense amplifiers
16
8,192
DATA
OUTPUT
REGISTER
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
256
(x16)
16
16
DQ0–
DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
