256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Functional Block Diagrams
Figure 3:
8 Meg x 32 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BA1
0
0
1
1
BA0
0
1
0
1
Bank
0
1
2
3
COMMAND
DECODE
BANK3
BANK2
BANK1
EXT MODE
REGISTER
MODE REGISTER
REFRESH 13
COUNTER
BANK0
ROW-
ADDRESS
4,096
LATCH
&
DECODER
14
12
ROW-
ADDRESS
MUX
12
BANK0
MEMORY
ARRAY
(4,096 x 512 x 32)
4
4
DQM0-
DQM3
SENSE AMPLIFIERS
32
4,096
DATA
OUTPUT
REGISTER
2
A0–A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
32
32
DQ0–
DQ31
512
(x32)
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
7
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©2006 Micron Technology, Inc. All rights reserved.
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