512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 34:
Power-Down Mode
T0
CLK
tCK
T1
tCL
tCKS
CKE
tCKS
tCKH
tCH
T2
((
))
((
))
((
))
((
))
Tn + 1
Tn + 2
tCKS
((
))
((
))
tCMS tCMH
COMMAND
PRECHARGE
NOP
NOP
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
NOP
ACTIVE
DQM/
DQML, DQMU
A0–A9,
A11, A12
ALL BANKS
ROW
A10
SINGLE BANK
((
))
((
))
ROW
tAS
BA0, BA1
tAH
((
))
((
))
((
))
BANK(S)
High-Z
((
))
((
))
((
))
BANK
DQ
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
Input buffers gated off while in
power-down mode
All banks idle
Exit power-down mode
Don’t Care
Note:
Violating refresh requirements during power-down may result in a loss of data.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
50
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