512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 38:
READ – Without Auto Precharge
T0
CLK
tCKS
CKE
tCMS
COMMAND
tCMH
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
T1
tCK
tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
tAS
BA0, BA1
tAH
ROW
tCMH
COLUMN
m
2
ROW
tAH
ROW
ALL BANKS
ROW
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
BANK
tAH
BANK
tAC
tAC
DQ
tLZ
tRCD
tRAS
tRC
CAS Latency
tOH
D
OUT
m
tAC
tOH
D
OUT
m
+ 1
tAC
tOH
D
OUT
m
+ 2
tOH
D
OUT
m
+ 3
tHZ
tRP
Don’t Care
Undefined
Notes:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
