512Mb: x4, x8, x16 SDRAM
General Description
Figure 2:
64 Meg x 8 SDRAM Functional Block Diagram
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
1
1
DQM
SENSE AMPLIFIERS
8
16384
DATA
OUTPUT
REGISTER
2
A0–A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
8
2048
(x8)
8
DQ0–
DQ7
2
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
11
11
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
7
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