128Mb: x4, x8, x16
SDRAM
CLK
CKE
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated (see Figure 3).
HIGH
CS#
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a tRCD specification
of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
BANK
ADDRESS
BA0, BA1
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimumtimeintervalbetweensuccessiveACTIVEcom-
mands to different banks is defined by tRRD.
Figure 3
Activating a Specific Row in a
Specific Bank
T0
T1
T2
T3
T4
CLK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD
DON’T CARE
Figure 4
t
t
t
<
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
15
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