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MT48LC16M8A2FC-7EL 参数 Datasheet PDF下载

MT48LC16M8A2FC-7EL图片预览
型号: MT48LC16M8A2FC-7EL
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 内存集成电路动态存储器时钟
文件页数/大小: 59 页 / 1835 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x4, x8, x16  
SDRAM  
READs  
READ bursts are initiated with a READ command, as  
shown in Figure 5.  
Upon completion of a burst, assuming no other com-  
mands have been initiated, the DQs will go High-Z. A full-  
page burst will continue until terminated. (At the end of  
the page, it will wrap to column 0 and continue.)  
Data from any READ burst may be truncated with a  
subsequentREADcommand,anddatafromafixed-length  
READ burst may be immediately followed by data from a  
READcommand. Ineithercase, acontinuousflowofdata  
can be maintained. The first data element from the new  
burst follows either the last element of a completed burst  
or the last desired data element of a longer burst that is  
being truncated. The new READ command should be  
issued x cycles before the clock edge at which the last  
desired data element is valid, where x equals the CAS  
latency minus one.  
The starting column and bank addresses are provided  
with the READ command, and auto precharge is either  
enabledordisabledforthatburstaccess.Ifautoprecharge  
is enabled, the row being accessed is precharged at the  
completion of the burst. For the generic READ com-  
mandsusedinthefollowingillustrations, autoprecharge  
is disabled.  
During READ bursts, the valid data-out element from  
the starting column address will be available following  
the CAS latency after the READ command. Each subse-  
quent data-out element will be valid by the next positive  
clock edge. Figure 6 shows general timing for each pos-  
sible CAS latency setting.  
T0  
T1  
T2  
T3  
CLK  
CLK  
CKE  
CS#  
HIGH  
COMMAND  
READ  
NOP  
t
NOP  
t
LZ  
OH  
DOUT  
DQ  
t
AC  
CAS Latency = 2  
RAS#  
CAS#  
WE#  
T0  
T1  
T2  
T3  
T4  
CLK  
COMMAND  
READ  
NOP  
NOP  
NOP  
t
t
LZ  
OH  
A0-A9, A11: x4  
A0-A9: x8  
COLUMN  
ADDRESS  
DOUT  
DQ  
A0-A8: x16  
t
AC  
A11: x8  
CAS Latency = 3  
A9, A11: x16  
DON’T CARE  
UNDEFINED  
ENABLE AUTO PRECHARGE  
DISABLE AUTO PRECHARGE  
A10  
Figure 6  
CAS Latency  
BANK  
ADDRESS  
BA0,1  
Figure 5  
READ Command  
128Mb: x4, x8, x16 SDRAM  
128MSDRAM_E.p65 Rev. E; Pub. 1/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2001, Micron Technology, Inc.  
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