64Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
Figure 3: 4 Meg x 16 Functional Block Diagram
CKE
CLK
CS#
WE#
CAS#
RAS#
Control logic
Command
decode
Bank 3
Bank 2
Bank 1
Mode register
12
Refresh
12
counter
Row-
address
MUX
12
12
Bank 0
row-
Bank 0
address
memory
4096
latch
array
and
(4096 x 256 x 16)
decoder
Sense amplifiers
4096
2
2
DQML,
DQMH
16
Data
output
register
16
2
A[11:0],
BA0, BA1
14
Address
register
2
Bank
control
logic
I/O gating
DQM mask logic
read data latch
write drivers
256
(x16)
DQ[15:0]
16
Data
input
register
Column
decoder
8
Column-
address
counter/
latch
8
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
10
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