64Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
Figure 2: 8 Meg x 8 Functional Block Diagram
CKE
CLK
CS#
WE#
CAS#
RAS#
Control logic
Command
decode
Bank 3
Bank 2
Bank 1
Mode register
12
Refresh
12
counter
Row-
address
MUX
12
12
Bank 0
row-
address
latch
4096
and
decoder
Bank 0
memory
array
(4096 x 512 x 8)
Sense amplifiers
4096
1
1
DQM
8
Data
output
register
8
2
A[11:0],
BA0, BA1
14
Address
register
2
Bank
control
logic
I/O gating
DQM mask logic
read data latch
write drivers
DQ[7:0]
512
(x8)
8
Data
input
register
9
Column-
address
counter/
latch
Column
decoder
9
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
9
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