128Mb: x32 SDRAM
Initialization
Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. After power is ap-
plied to V
DD
and V
DDQ
(simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-
quires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or
NOP. Starting at some point during this 100μs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands must be applied.
After the 100μs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH com-
mands can be issued after the LMR command.
The recommended power-up sequence for SDRAM:
1. Simultaneously apply power to V
DD
and V
DDQ
.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin.
4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIB-
IT or NOP.
5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at
least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-
mands must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least
t
RP time; during this time NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode reg-
ister will power up in an unknown state, it should be loaded with desired bit values
prior to applying any operational command. Using the LMR command, program
the mode register. The mode register is programmed via the MODE REGISTER SET
command with BA1 = 0, BA0 = 0 and retains the stored information until it is pro-
grammed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Out-
puts are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
13. Wait at least
t
MRD time, during which only NOP or DESELECT commands are al-
lowed.
At this point the DRAM is ready for any valid command.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
35
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2001 Micron Technology, Inc. All rights reserved.
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