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MT48LC4M32B2P 参数 Datasheet PDF下载

MT48LC4M32B2P图片预览
型号: MT48LC4M32B2P
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC4M32B2 â ???? 1梅格×32× 4银行 [SDR SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 80 页 / 4594 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x32 SDRAM  
Features  
List of Figures  
Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 7  
Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 8  
Figure 3: 90-Ball FBGA Ball Assignments (Top View) ......................................................................................... 9  
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Revision L ..................................................................................... 11  
Figure 5: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12  
Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 13  
Figure 7: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 15  
Figure 8: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 16  
Figure 9: ACTIVE Command .......................................................................................................................... 25  
Figure 10: READ Command ........................................................................................................................... 26  
Figure 11: WRITE Command ......................................................................................................................... 27  
Figure 12: PRECHARGE Command ................................................................................................................ 28  
Figure 13: Initialize and Load Mode Register .................................................................................................. 37  
Figure 14: Mode Register Definition ............................................................................................................... 39  
Figure 15: CAS Latency .................................................................................................................................. 42  
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Figure 16: Example: Meeting tRCD (MIN) When 2 < RCD (MIN)/tCK < 3 .......................................................... 43  
Figure 17: Consecutive READ Bursts .............................................................................................................. 45  
Figure 18: Random READ Accesses ................................................................................................................ 46  
Figure 19: READ-to-WRITE ............................................................................................................................ 47  
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48  
Figure 21: READ-to-PRECHARGE .................................................................................................................. 48  
Figure 22: Terminating a READ Burst ............................................................................................................. 49  
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 50  
Figure 24: READ Continuous Page Burst ......................................................................................................... 51  
Figure 25: READ – DQM Operation ................................................................................................................ 52  
Figure 26: WRITE Burst ................................................................................................................................. 53  
Figure 27: WRITE-to-WRITE .......................................................................................................................... 54  
Figure 28: Random WRITE Cycles .................................................................................................................. 55  
Figure 29: WRITE-to-READ ............................................................................................................................ 55  
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 56  
Figure 31: Terminating a WRITE Burst ............................................................................................................ 57  
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 58  
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 59  
Figure 34: WRITE – DQM Operation ............................................................................................................... 60  
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 62  
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63  
Figure 37: READ With Auto Precharge ............................................................................................................ 64  
Figure 38: READ Without Auto Precharge ....................................................................................................... 65  
Figure 39: Single READ With Auto Precharge .................................................................................................. 66  
Figure 40: Single READ Without Auto Precharge ............................................................................................. 67  
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68  
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68  
Figure 43: WRITE With Auto Precharge ........................................................................................................... 69  
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 70  
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 71  
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 72  
Figure 47: Auto Refresh Mode ........................................................................................................................ 74  
Figure 48: Self Refresh Mode .......................................................................................................................... 76  
Figure 49: Power-Down Mode ........................................................................................................................ 77  
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 78  
PDF: 09005aef80872800  
128mb_x32_sdram.pdf - Rev. P 9/11 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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