16Mb: 1 MEG x16
EDO DRAM
NOTES
1. All voltages referenced to V
SS
.
2. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0ºC
£
T
A
£
70ºC for
commercial) and (-20ºC
£
T
A
£
80ºC for extended)
is ensured.
3. An initial pause of 100µs is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
4. NC pins are assumed to be left floating and are
not tested for leakage.
5. I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
9. AC characteristics assume
t
T = 2.5ns.
10.V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
(or
between V
IL
and V
IH
).
11.In addition to meeting the transition rate
specification, all input signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
12.Measured with a load equivalent to two TTL gates
and 100pF; and V
OL
= 0.8V and V
OH
= 2V.
t
WCS,
t
RWD,
t
AWD, and
t
CWD are not restrictive
13.
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit through-
out the entire cycle. If
t
WCS <
t
WCS (MIN) and
t
RWD
t
RWD (MIN),
t
AWD
t
AWD (MIN) and
t
CWD
t
CWD (MIN), the cycle is a READ-
MODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW results in a LATE
WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD
and
t
AWD are not applicable in a LATE WRITE
cycle.
14.Assumes that
t
RCD
t
RCD (MAX).
15.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
t
CP.
16.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
17.If OE# is tied permanently LOW, LATE WRITE, or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, WE# must be pulsed during CAS#
HIGH time in order to place I/O buffers in High-Z.
18.LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
t
OEH is met. If CAS# goes HIGH prior to
OE# going back LOW, the DQs will remain open.
19.Assumes that
t
RCD <
t
RCD (MAX). If
t
RCD is
greater than the maximum recommended value
shown in this table,
t
RAC will increase by the
amount that
t
RCD exceeds the value shown.
20.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21.The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively
by
t
AA (
t
RAC and
t
CAC no longer applied). With or
without the
t
RAD (MAX) limit,
t
AA,
t
RAC, and
t
CAC
must always be met.
22.The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively
by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD limit,
t
AA and
t
CAC must always
be met.
23.Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
24.The first CAS#x edge to transition LOW.
25.Output parameter (DQx) is referenced to corre-
sponding CAS# input; DQ0-DQ7 by CASL# and
DQ8-DQ15 by CASH#.
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc
MICRON [ MICRON TECHNOLOGY ]
