16Mb: 1 MEG x16
EDO DRAM
NOTES (continued)
26.Each CAS#x must meet minimum pulse width.
27.The last CAS#x edge to transition HIGH.
28.Last falling CAS#x edge to first rising CAS#x edge.
29.Last rising CAS#x edge to first falling CAS#x edge.
30.Last rising CAS#x edge to next cycle’s last rising
CAS#x edge.
31.Last CAS#x to go LOW.
32.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
11
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©2001, Micron Technology, Inc
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