16Mb: 1 MEG x16
EDO DRAM
READ CYCLE
tRC
tRAS
V IH
V IL
tCSH
tRSH
tCRP
V IH
V IL
tAR
tASR
tRAD
tRAH
tASC
tCAH
tACH
ADDR
V IH
V IL
ROW
tRCS
WE#
V IH
V IL
tAA
tRAC
tCAC
tCLZ
DQ
V OH
V OL
COLUMN
tRCH
ROW
tRCD
tCAS
tCLCH
tRRH
tRP
RAS#
CASL#/CASH#
NOTE 1
tOFF
OPEN
tOE
VALID DATA
tOD
OPEN
OE#
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
t
AA
t
ACH
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CLCH
t
CLZ
t
CRP
t
CSH
t
OD
-6
MAX
25
MIN
15
45
0
0
13
15
10
10
5
0
5
45
0
10,000
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
OE
t
OFF
t
RAC
t
RAD
t
RAH
t
RAS
t
RC
t
RCD
t
RCH
t
RCS
t
RP
t
RRH
t
RSH
-5
MIN
0
9
9
50
84
11
0
0
30
0
13
10,000
MAX
12
12
50
MIN
0
12
10
60
104
14
0
0
40
0
15
-6
MAX
15
15
60
UNITS
ns
ns
ns
ns
ns
10,000
ns
ns
ns
ns
ns
ns
ns
ns
MIN
12
38
0
0
8
8
5
0
5
38
0
10,000
12
15
NOTE:
1.
t
OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc
MICRON [ MICRON TECHNOLOGY ]
