N25Q128 - 1.8 V
Instructions
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
cycle or Erase cycle continues unaffected, the only exception is the Program/Erase
Suspend instruction (PES), that can be used to pause all the program and the erase cycles
but the Program OTP (POT), Bulk Erase (BE) and Write Non Volatile Configuration Register.
The suspended program or erase cycle can be resumed by mean of the Program/Erase
Resume instruction (PER). During the program/erase cycles also the polling instructions (to
check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or
of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the
application checking the end of the internal modify cycles, of course these polling
instructions don't affect the internal cycles performing.
Table 24.
Instruction set: QIO-SPI protocol (page 1 of 2)
One-byte
Instruction
Code (BIN)
1010 1111
0000 1011
QCFR
Quad Command Fast Read
0110 1011
1110 1011
ROTP
WREN
WRDI
Read OTP (Read of OTP area)
Write Enable
Write Disable
0100 1011
0000 0110
0000 0100
0000 0010
QCPP
Quad Command Page Program
0011 0010
0001 0010
POTP
SSE
(2)
SE
BE
PER
PES
RDSR
WRSR
RDLR
WRLR
RFSR
CLFSR
RDNVCR
Program OTP (Program of OTP
area)
SubSector Erase
Sector Erase
Bulk Erase
Program/Erase Resume
Program/Erase Suspend
Read Status Register
Write Status Register
Read Lock Register
Write to Lock Register
Read Flag Status Register
Clear Flag Status Register
Read NV Configuration Register
0100 0010
0010 0000
1101 1000
1100 0111
0111 1010
0111 0101
0000 0101
0000 0001
1110 1000
1110 0101
0111 0000
0101 0000
1011 0101
One-byte
Dummy
Instruction Address
clock
Code
bytes
cycle
(HEX)
AFh
0Bh
6Bh
EBh
4Bh
06h
04h
02h
32h
12h
42h
20h
D8h
C7h
7Ah
75h
05h
01h
E8h
E5h
70h
50h
B5h
0
3
3
3
3
0
0
3
3
3
3
3
3
0
0
0
0
0
3
3
0
0
0
0
10
(1)
10
(1)
10
(1)
10
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
bytes
1 to 3
1 to
∞
1 to
∞
1 to
∞
1 to 65
0
0
1 to 256
1 to 256
1 to 256
1 to 65
0
0
0
0
0
1 to
∞
1
1 to
∞
1
1 to
∞
0
2
Instruction
Description
MIORDID
Multiple I/O read identification
133/185
MICRON [ MICRON TECHNOLOGY ]
