N25Q128 - 1.8 V
Table 4.
Bit
Volatile and Non Volatile Registers
Non-Volatile Configuration Register
Parameter
Value
111
0
Enabled
Disabled (default)
disabled
Disable Pad Hold/Reset functionality
1
0
1
0
1
xx
enabled (default)
enabled
Enable command on four input line
disabled (default)
enabled
Enable command on two input line
disabled (default)
Don't care
Default value = "11"
Fast POR x
READ
Reset/Hold
disable
Quad Input
Command
Dual Input
Command
Reserved
Description
30 (default)
POR phase < 100us only read available
POR phase ~ 700us all instructions
available
Note
NVCR<5>
1
0
NVCR<4>
NVCR<3>
NVCR<2>
NVCR<1:0>
6.2.1
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 5.
Maximum allowed frequency (MHz)
Maximum allowed frequency (MHz)
(1)
Dummy Clock
1
2
3
4
5
6
7
8
9
10
FASTREAD
50
95
105
108
108
108
108
108
108
108
DOFR
50
85
95
105
108
108
108
108
108
108
DIOFR
39
59
75
88
94
105
108
108
108
108
QOFR
43
56
70
83
94
105
108
108
108
108
QIOFR
20
39
49
59
69
78
86
95
105
108
1. All values are guaranteed by characterization and not 100% tested in production.
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MICRON [ MICRON TECHNOLOGY ]
