Instructions
N25Q128 - 1.8 V
polling instructions (to check if the internal cycle is finished by mean of the WIP bit of the
Status Register or of the Program/Erase controller bit of the Flag Status register): to verify if
the POR sequence is completed is possible to check the WIP bit in the Status Register or
the Program/Erase Controller bit in the Flag Status Register, please note that the
Program/Erase Controller bit in the Flag status register has the reverse logical polarity with
respect to the Status Register WIP bit.
At the end of the POR sequence the WEL bit is low, so the next modify instruction can be
accepted.
Figure 18. Write Enable instruction sequence
S
0
C
Instruction
DQ0
High Impedance
DQ1
AI13731
1
2
3
4
5
6
7
9.1.10
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
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