N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128 - 1.8 V

The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Write lo Lock Register (WRLR) instruction completion

Instructions

Write Non Volatile Configuration Register (WRNVCR) instruction completion

Write Volatile Configuration Register (WRVCR) instruction completion

Write Volatile Enhanced Configuration Register (WRVECR) instruction completion

Page Program (PP) instruction completion

Dual Input Fast Program (DIFP) instruction completion

Dual Input Extended Fast Program (DIEFP) instruction completion

Quad Input Fast Program (QIFP) instruction completion

Quad Input Extended Fast Program (QIEFP) instruction completion

Program OTP (POTP) instruction completion

Subsector Erase (SSE) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

Figure 19. Write Disable instruction sequence

S

0

C

Instruction

DQ0

High Impedance

DQ1

AI13732

1

2

3

4

5

6

7

9.1.11

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes and at least one data byte on Serial Data input

(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that

goes beyond the end of the current page are programmed from the start address of the

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