512Mb, Multiple I/O Serial Flash Memory
Device Description
Device Description
The N25Q is a high-performance multiple input/output serial Flash memory device
manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionali-
ty, advanced write protection mechanisms, and a high-speed SPI-compatible bus inter-
face. Innovative, high-performance, dual and quad input/output instructions enable
double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Features
The 512Mb N25Q stacked device contains two 256Mb die. From a user standpoint this
stacked device behaves as a monolithic device, except with regard to READ MEMORY
and ERASE operations and status polling. The device contains a single chip select (S#); a
dual-chip version is also available. Contact the factory for more information.
The memory is organized as 1024 (64KB) main sectors that are further divided into 16
subsectors each (16,384 subsectors in total). The memory can be erased one 4KB sub-
sector at a time, 64KB sectors at a time, or single die (256Mb) at a time.
The memory can be write protected by software through volatile and nonvolatile pro-
tection features, depending on the application needs. The protection granularity is of
64KB (sector granularity) for volatile protections
The device has 64 one-time programmable (OTP) bytes that can be read and program-
med with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be
permanently locked with a PROGRAM OTP command.
The device can also pause and resume PROGRAM and ERASE cycles by using dedicated
PROGRAM/ERASE SUSPEND and RESUME instructions.
3-Byte Address and 4-Byte Address Modes
The device features 3-byte or 4-byte address modes to access memory beyond 128Mb.
When 4-byte address mode is enabled, all commands requiring an address must be en-
tered and exited with a 4-byte address mode command: ENTER 4-BYTE ADDRESS
MODE command and EXIT 4-BYTE ADDRESS MODE command. The 4-byte address
mode can also be enabled through the nonvolatile configuration register. See Registers
for more information.
Operating Protocols
The memory can be operated with three different protocols:
• Extended SPI (standard SPI protocol upgraded with dual and quad operations)
• Dual I/O SPI
• Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In
addition, the dual SPI and quad SPI protocols improve the data access time and
throughput of a single I/O device by transmitting commands, addresses, and data
across two or four data lines.
Each protocol contains unique commands to perform READ operations in DTR mode.
This enables high data throughput while running at lower clock frequencies.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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2011 Micron Technology, Inc. All rights reserved.
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