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    N25Q512A13GF840E 参数 Datasheet PDF下载

    N25Q512A13GF840E图片预览
    型号： N25Q512A13GF840E
    PDF下载： 下载PDF文件 查看货源
    内容描述： 美光的串行NOR闪存3V ，多个I / O， 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
    分类和应用： 闪存
    文件页数/大小： 91 页 / 1214 K
    品牌： MICRON [ MICRON TECHNOLOGY ]
     浏览型号N25Q512A13GF840E的Datasheet PDF文件第1页浏览型号N25Q512A13GF840E的Datasheet PDF文件第2页浏览型号N25Q512A13GF840E的Datasheet PDF文件第3页浏览型号N25Q512A13GF840E的Datasheet PDF文件第5页浏览型号N25Q512A13GF840E的Datasheet PDF文件第6页浏览型号N25Q512A13GF840E的Datasheet PDF文件第7页浏览型号N25Q512A13GF840E的Datasheet PDF文件第8页浏览型号N25Q512A13GF840E的Datasheet PDF文件第9页  
    512Mb, Multiple I/O Serial Flash Memory
    Features
    List of Figures
    Figure 1: Logic Diagram ................................................................................................................................... 7
    Figure 2: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8
    Figure 3: 24-Ball TBGA (Balls Down) ................................................................................................................ 8
    Figure 4: Block Diagram ................................................................................................................................ 11
    Figure 5: Bus Master and Memory Devices on the SPI Bus ............................................................................... 16
    Figure 6: SPI Modes ....................................................................................................................................... 16
    Figure 7: Internal Configuration Register ........................................................................................................ 18
    Figure 8: Upper and Lower Memory Array Segments ....................................................................................... 23
    Figure 9: READ REGISTER Command ............................................................................................................ 32
    Figure 10: WRITE REGISTER Command ......................................................................................................... 34
    Figure 11: READ LOCK REGISTER Command ................................................................................................. 37
    Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 38
    Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 40
    Figure 14: READ Command ........................................................................................................................... 47
    Figure 15: FAST READ Command ................................................................................................................... 47
    Figure 16: DUAL OUTPUT FAST READ Command .......................................................................................... 48
    Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 48
    Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 49
    Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 49
    Figure 20: FAST READ Command – DTR ......................................................................................................... 50
    Figure 21: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 51
    Figure 22: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 51
    Figure 23: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 52
    Figure 24: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 52
    Figure 25: PAGE PROGRAM Command .......................................................................................................... 54
    Figure 26: DUAL INPUT FAST PROGRAM Command ...................................................................................... 55
    Figure 27: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 55
    Figure 28: QUAD INPUT FAST PROGRAM Command ..................................................................................... 56
    Figure 29: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 57
    Figure 30: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 59
    Figure 31: SUBSECTOR and SECTOR ERASE Command .................................................................................. 61
    Figure 32: DIE ERASE Command ................................................................................................................... 62
    Figure 33: BULK ERASE Command ................................................................................................................ 64
    Figure 34: RESET ENABLE and RESET MEMORY Command ........................................................................... 67
    Figure 35: READ OTP Command .................................................................................................................... 68
    Figure 36: PROGRAM OTP Command ............................................................................................................ 69
    Figure 37: XIP Mode Directly After Power-On .................................................................................................. 72
    Figure 38: Power-Up Timing .......................................................................................................................... 74
    Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 77
    Figure 40: Reset Enable ................................................................................................................................. 77
    Figure 41: Serial Input Timing ........................................................................................................................ 77
    Figure 42: Hold Timing .................................................................................................................................. 78
    Figure 43: Output Timing .............................................................................................................................. 78
    Figure 44: V
    PPH
    Timing .................................................................................................................................. 79
    Figure 45: AC Timing Input/Output Reference Levels ...................................................................................... 81
    Figure 46: V-PDFN-8/8mm x 6mm ................................................................................................................. 85
    Figure 47: SOP2-16/300 mils .......................................................................................................................... 86
    Figure 48: T-PBGA-24b05/6mm x 8mm .......................................................................................................... 87
    PDF: 09005aef84752721
    n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
    4
    Micron Technology, Inc. reserves the right to change products or specifications without notice.
    ©
    2011 Micron Technology, Inc. All rights reserved.

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