128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Table 55: AADM Asynchronous and Latching Timings (Continued)
Symbol
t
GHVH
t
GLVH
t
VHGH
MIN (ns)
3
3
3
Notes:
MAX (ns)
Notes
1. A READ cycle may be restarted prior to completing a pending READ operation, but this
may occur only once before the sense operation is allowed to complete.
2.
t
VHQV applies to asynchronous read access time.
Figure 51: AADM Asynchronous READ Cycle (Latching A[MAX:0])
A/DQ[15:0]
A[MAX:16]
t
AVVH
t
VLVH
t
VHAX
t
VHVL
A[15:0]
t
AVVH
t
VLVH
t
VHAX
t
VHQV
DQ[15:0]
ADV#
t
EHQZ
t
ELVH
t
EHEL
CE#
t
GLVH
t
VHGH
t
GHVH
t
VHGL
t
GLQX
t
GLQV
t
GHQZ
t
GHVH
+
t
VHGL
OE#
t
GLTV
t
GLTX
t
GHTZ
t
EHTZ
WAIT
Notes:
1. CE# need not be de-asserted at beginning of the cycle if OE# does not have output con-
trol.
2. Diagram shows WAIT as active LOW (RCR[10] = 0).
Figure 52: AADM Asynchronous READ Cycle (Latching A[15:0] only)
A/DQ[15:0]
A[15:0]
t
AVVH
t
VLVH
t
VHAX
t
VHQV
DQ[15:0]
ADV#
t
EHQZ
t
ELVH
t
EHEL
CE#
t
VHGL
t
GLQX
t
GLQV
t
GHQZ
t
VHGH
+
t
GHVL
OE#
t
GLTV
t
GLTX
t
GHTZ
t
EHTZ
WAIT
Notes:
1. Diagram shows WAIT as active LOW (RCR[10] = 0).
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
111
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