128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Figure 56: AADM Synchronous Burst READ Cycle (ADV# Not De-asserted Between Address Cycles)
A/DQ[15:0]
A[MAX:16]
t
AVCH
t
CHAX
A[15:0]
t
AVCH
t
CHAX
DQ[15:0]
DQ[15:0]
A
Latency count
t
CHQV
t
CHQX
CLK
t
CHVL
t
VLCH
t
CHVH
ADV#
t
ELCH
CE#
t
GHCH
t
GLCH
t
CHGH
t
CHGL
OE#
WE#
t
GLTX
t
GLTV
t
CHTV
t
CHTX
WAIT
Notes:
1. CE# need not be de-asserted at beginning of cycle if OE# does not have output control.
2. Diagram shows WAIT as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
3. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown).
Figure 57: AADM Synchronous Burst READ Cycle (Latching A[15:0] only)
A/DQ[15:0]
A[15:0]
DQ[15:0]
DQ[15:0]
A
Latency count
t
AVCH
t
CHAX
t
CHQV
t
CHQX
CLK
t
CHVL
t
VLCH
t
CHVH
ADV#
t
ELCH
CE#
t
CHGL
OE#
WE#
t
GLTX
t
GLTV
t
CHTV
t
CHTX
WAIT
Notes:
1. Diagram shows WAIT as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
2. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown).
3. Without latching A[MAX:16] in the synchronous READ cycle, the previously latched
A[MAX:16] applies.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
115
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