128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Signal Descriptions
Signal Descriptions
Table 4: Signal Descriptions
Symbol
Non-MUX
A[MAX:1]
DQ[15:0]
A/D MUX
A[MAX:17]
ADQ[15:0]
Input
Input/Output
Address inputs:
Upper address inputs for all READ/WRITE cycles.
Address or data:
Lower address inputs during the address phase for all READ/WRITE
cycles; data or command inputs during WRITE cycles; data, status, or device informa-
tion outputs during READ cycles.
Chip enable:
LOW true input. When LOW, CE# selects the die; when HIGH, CE# dese-
lects the die and places it in standby.
Output enable:
LOW true input. Must be LOW for READs and HIGH for WRITEs.
Write enable:
LOW true input. Must be LOW for WRITEs and HIGH for READs.
Clock:
Synchronizes burst READ operations with the host controller.
Address valid:
LOW true input. When LOW, ADV# enables address inputs. For syn-
chronous burst READs, address inputs are latched on the rising edge.
Write protect:
LOW true input. When LOW, WP# enables block lock down; when
HIGH, WP# disables block lock down.
Reset:
LOW true input. When LOW, RST# inhibits all operations; must be HIGH for
normal operations.
Erase/program voltage:
Enables voltage for PROGRAM and ERASE operations. Array
contents cannot be altered when V
PP
is at or below V
PPLK
.
WAIT:
Configurable HIGH or LOW true output. When asserted, WAIT indicates
DQ[15:0] is invalid; when de-asserted, WAIT indicates DQ[15:0] is valid.
Core power:
Supply voltage for core circuits. All operations are inhibited when V
CC
is
at or below V
LKO
.
I/O power:
Supply voltage for all I/O drivers. All operations are inhibited when V
CCQ
is
at or below V
LKOQ
.
Logic ground:
Core logic ground return. Connect all V
SS
balls to system ground; do
not float any V
SS
balls.
I/O ground:
I/O driver ground return. Connect all V
SSQ
balls to system ground; do not
float any V
SSQ
balls.
Input
Input/Output
Address inputs:
Address inputs for all READ/WRITE cycles.
Data:
Data or command inputs during WRITE cycles; data, status, or device informa-
tion outputs during READ cycles.
Type
Description
Control Signals
CE#
OE#
WE#
CLK
ADV#
WP#
RST#
V
PP
WAIT
V
CC
V
CCQ
V
SS
V
SSQ
Input
Input
Input
Input
Input
Input
Input
Input
Output
Power
Power
Power
Power
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
15
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