128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Bus Interface
Asynchronous Read
For RCR15 = 1 (default), CE# LOW and OE# LOW place the device in asynchronous bus
read mode:
•
•
•
•
RST# and WE# must be held HIGH; CLK must be tied either HIGH or LOW.
Address inputs must be held stable throughout the access, or latched with ADV#.
ADV# must be held LOW or can be toggled to latch the address.
Valid data is output on the data I/Os after
t
AVQV,
t
ELQV,
t
VLQV, or
t
GLQV, whichever is
satisfied last.
Asynchronous READ operations are independent of the voltage level on V
PP
.
For asynchronous page reads, subsequent data words are output
t
APA after the least sig-
nificant address bit(s) are toggled: 16-word page buffer, A[3:0].
Synchronous Read
For RCR15 = 0, CE# LOW, OE# LOW, and ADV# LOW place the device in synchronous
bus read mode:
•
•
•
•
RST# and WE# must be held HIGH.
CLK must be running.
The first data word is output
t
CHQV after the latency count has been satisfied.
For array reads, the next address data is output
t
CHQV after valid CLK edges until the
burst length is satisfied.
• For nonarray reads, the same address data is output
t
CHQV after valid CLK edges until
the burst length is satisfied.
The address for synchronous read operations is latched on the ADV# rising edge or the
first rising CLK edge after ADV# low, whichever occurs first for devices that support up
to 108 MHz. For devices that support up to 133 MHz, the address is latched on the last
CLK edge when ADV# is low.
Burst Wrapping
Data stored within the memory array is arranged in rows or word lines. During synchro-
nous burst reads, data words are sensed in groups from the array. The starting address
of a synchronous burst read determines which word within the wordgroup is output
first, and subsequent words are output in sequence until the burst length is satisfied.
The setting of the burst wrap bit (RCR3) determines whether synchronous burst reads
will wrap within the wordgroup or continue on to the next wordgroup.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
18
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2011 Micron Technology, Inc. All rights reserved.
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