256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operation
and BEFP operation terminates. If the block was found to be locked, SR.1 is also set. SR.
3 is set if the error occurred due to an incorrect V
PP
level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence
outputs status register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7 cleared
indicates the device is busy and the BEFP program/verify phase is activated. SR.0 indi-
cates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 512 words. During the buffer-loading sequence, data is stor-
ed to sequential buffer locations starting at address 0x00. Programming of the buffer
contents to the flash memory array starts as soon as the buffer is full. If the number of
words is less than 512, the remaining buffer locations must be filled with 0xFFFF.
Note:
The buffer must be completely filled for programming to occur. Supplying an ad-
dress outside of the current block's range during a buffer-fill sequence causes the algo-
rithm to exit immediately. Any data previously loaded into the buffer during the fill cy-
cle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP algo-
rithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer pro-
gram sequence completes. SR.0 cleared indicates that all buffer data has been transfer-
red to the flash array; SR.0 set indicates that the buffer is not available yet for the next
fill cycle. The host system may check full status for errors at any time, but it is only nec-
essary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should
be issued to the device until SR.0 = 0 and the device is ready for the next buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal
program is proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this phase
by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed success-
fully. When exiting the BEFP algorithm with a block address change, the read mode will
not change. After BEFP exit, any valid command can be issued to the device.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
35
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