256Mb and 512Mb (256Mb/256Mb), P30-65nm
One-Time Programmable Registers
Figure 16: OTP Register Map
0x109
128-bit OTP
Register 16
User Programmable
0x102
0x91
128-bit OTP
Register 1
User Programmable
0x8A
Lock Register 1
0x89
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0x88
128-bit OTP
Register 0
0x85
0x84
0x81
64-bit Segment
User Programmable
64-bit Segment
Factory Programed
Lock Register 0
0x80
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Program OTP Registers
To program an OTP register, a PROGRAM OTP REGISTER command is issued at the pa-
rameter’s base address plus the offset of the desired OTP register location. Next, the de-
sired OTP register data is written to the same OTP register address.
The device programs the 64-bit and 128-bit user-programmable OTP register data 16
bits at a time. Issuing the PROGRAM OTP REGISTER command outside of the OTP reg-
ister’s address space causes a program error (SR4 set). Attempting to program a locked
OTP register causes a program error (SR4 set) and a lock error (SR1 set).
Lock OTP Registers
Each OTP register can be locked by programming its respective lock bit in the lock regis-
ter. The corresponding bit in the lock register is programmed by issuing the PROGRAM
LOCK REGISTER command, followed by the desired lock register data. The physical ad-
dresses of the lock registers are 0x80 for register 0 and 0x89 for register 1; these address-
es are used when programming the lock registers.
Bit 0 of lock register 0 is programmed during the manufacturing process, locking the
lower-half segment of the first 128-bit OTP register. Bit 1 of lock register 0, which corre-
sponds to the upper-half segment of the first 128-bit OTP register, can be programmed
by the user . When programming bit 1 of lock register 0, all other bits need to be left as 1
such that the data programmed is 0xFFFD.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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