256Mb and 512Mb (256Mb/256Mb), P30-65nm
Power and Reset Specifications
Power and Reset Specifications
V
CC
should attain V
CCmin
from V
SS
simultaneously with or before applying V
CCQ
, V
PP
during power up. V
CC
should attain V
SS
during power down. Device inputs should not
be driven before supply voltage = V
CCmin
.
Power supply transitions should only occur when RST# is LOW. This protects the device
from accidental programming or erasure during power transitions.
Asserting RST# during a system reset is important with automated program/erase devi-
ces because systems typically expect to read from the device when coming out of reset.
If a CPU reset occurs without a device reset, proper CPU initialization may not occur.
This is because the device may be providing status information, instead of array data as
expected. Connect RST# to the same active LOW reset signal used for CPU initialization.
Because the device is disabled when RST# is asserted, it ignores its control inputs dur-
ing power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 37: Power and Reset
Parameter
RST# pulse width LOW
RST# LOW to device reset during erase
RST# LOW to device reset during program
V
CC
Power valid to RST# de-assertion (HIGH)
Notes:
1.
2.
3.
4.
5.
t
VCCPH
Symbol
t
PLPH
t
PLPH
Min
100
–
–
300
Max
–
25
25
–
Unit
ns
us
Notes
1, 2, 3, 4
1, 3, 4, 7
1, 3, 4, 7
1, 4, 5, 6
These specifications are valid for all device versions (packages and speeds).
The device may reset if
t
PLPH is <
t
PLPH MIN, but this is not guaranteed.
Not applicable if RST# is tied to V
CC
.
Sampled, but not 100% tested.
When RST# is tied to the V
CC
supply, device will not be ready until
t
VCCPH after V
CC
≥
V
CCMIN
.
6. When RST# is tied to the V
CCQ
supply, device will not be ready until
t
VCCPH after V
CC
≥
V
CCMIN
.
7. Reset completes within
t
PLPH if RST# is asserted while no ERASE or PROGRAM operation
is executing.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
77
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