512Mb, 1Gb, 2Gb: P30-65nm
AC Read Specifications
Table 39: AC Read Specifications (Continued)
Parameter
Symbol
tCLK
tCLK
tCH/CL
tFCLK/RCLK
Min
–
Max
Unit
MHz
ns
Notes
CLK frequency
CLK period
52
–
1, 3, 5, 6
19.2
5
CLK HIGH/LOW time
CLK fall/rise time
–
ns
0.3
3
ns
Synchronous Specifications (Easy BGA)5
Address setup to CLK
ADV# LOW setup to CLK
CE# LOW setup to CLK
CLK to output valid
tAVCH/L
tVLCH/L
tELCH/L
tCHQV /
tCLQV
9
9
9
–
–
–
ns
ns
ns
ns
1, 6
–
17
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
3
10
–
-
-
ns
ns
ns
ns
ns
1, 6
1, 4, 6
1, 6
1
17
–
CLK valid to ADV# setup
WAIT hold from CLK
3
3
–
1, 6
1. See AC Test Conditions for timing measurements and maximum allowable input slew
rate.
Notes:
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to
tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specifica-
tion is satisfied first.
5. Synchronous read mode is not supported with TTL level inputs.
6. Applies only to subsequent synchronous reads.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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