512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Table 14: End of Wordline Data and WAIT State Comparison
130nm
Latency Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Data Words
Not Supported
4
4
4
4
4
4
Not Supported
WAIT States
Not Supported
0 to 1
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
Not Supported
Data Words
Not Supported
Not Supported
Not Supported
Not Supported
16
16
16
16
16
16
16
16
16
16
16
65nm
WAIT States
Not Supported
Not Supported
Not Supported
Not Supported
0 to 4
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
WAIT Signal Polarity and Functionality
The WAIT polarity (WP) bit, RCR10 determines the asserted level (V
OH
or V
OL
) of WAIT.
When WP is set, WAIT is asserted HIGH (default). When WP is cleared, WAIT is asserted
LOW. The WAIT signal changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# de-asserted).
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR15 = 0). The WAIT signal is only de-asserted when data is valid on the bus. When
the device is operating in synchronous nonarray read mode, such as read status, read
ID, or read CFI, the WAIT signal is also de-asserted when data is valid on the bus. WAIT
behavior during synchronous nonarray reads at the end of wordline works correctly on-
ly on the first data access. When the device is operating in asynchronous page mode,
asynchronous single word read mode, and all write operations, WAIT is set to a de-as-
serted state as determined by RCR10.
Table 15: WAIT Functionality Table
Condition
CE# = 1, OE# = X or CE# = 0, OE# = 1
CE# = 0, OE# = 0
Synchronous Array Reads
Synchronous Nonarray Reads
All Asynchronous Reads
WAIT
High-Z
Active
Active
Active
De-asserted
Notes
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
42
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