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ACE9030M/IW/FP1N 参数 Datasheet PDF下载

ACE9030M/IW/FP1N图片预览
型号: ACE9030M/IW/FP1N
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 电信集成电路无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030
ABSOLUTE MAXIMUM RATINGS
Supply voltage from ground
– 0·3 V to + 6·0 V
(any V
DD
to any V
SS
)
Supply voltage difference
– 0·3 V to + 0·3 V
(any V
DD
to any other V
DD
)
Input voltage
V
SS
– 0·3 V to V
DD
+ 0·3 V
(any input pin to its local V
SS
and V
DD
)
Output voltage
V
SS
– 0·3 V to V
DD
+ 0·3 V
(any output pin to its local V
SS
and V
DD
)
Storage temperature
– 55
°C
to + 150
°C
Operating temperature
– 40
°C
to + 85
°C
These are not the operating conditions, but are the
absolute limits which if exceeded even momentarily may
cause permanent damage. To ensure sustained correct op-
eration the device should be used within the limits given under
Electrical Characteristics.
To avoid any possibility of latch-up the substrate connec-
tions V
DDSUB
and V
DDSUB2
must be the most positive of all V
DD
’s
at all times including during power on and off ramping. As the
current taken through these V
DD
’s is significantly less than
through the other V
DD
’s this requirement can be easily met by
directly connecting all V
DD
pins to a common point on the
circuit board but with the decoupling capacitors distributed to
minimise cross-talk caused by common mode currents. If low
value series resistors are to be included in the V
DD
connec-
tions, with decoupling capacitors by the ACE9030 pins to
further reduce interference, the V
DDSUB
and V
DDSUB2
pins should
not have such a resistor in order to guarantee that their
voltage is not slowed down at power-on. Power switches to
DOUT0 and DOUT1 are supplied from V
DDX
and are specified
for a total current of up to 40 mA so any resistor in the V
DDX
connection must be very low, around 1Ω, in order to avoid
excessive voltage drop; it is recommended that this supply
has no series resistor. These two methods are shown in circuit
diagrams, figures 4 and 5. In both circuits the main V
DD
must
also have good decoupling.
Main VDD
VDDSUB
VDDSUB2
VDDL
VDDA
VDDX
VDDD
VDDSA
Fig.4 Typical VDD local decoupling networks without series resistors
Main VDD
No Resistor
VDDSUB
No Resistor
VDDSUB2
VDDL
VDDA
Very
Small
VDDX
VDDD
VDDSA
Fig.5 Typical VDD local decoupling networks with series resistors
4