MT8888C/MT8888C-1
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
V
DD
MT8888C/
MT8888C-1
V
DD
St/GT
ESt
R1
C1
Vc
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
t
REC
≥
t
DPmax
+t
GTPmax
- t
DAmin
t
REC
≤
t
DPmin
+t
GTPmin
- t
DAmax
t
ID
≥
t
DAmax
+t
GTAmax
- t
DPmin
t
DO
≤
t
DAmin
+t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
t
GTP
= (R
P
C1) In [V
DD
/ (V
DD
-V
TSt
)]
t
GTA
= (R1C1) In (V
DD
/V
TSt
)
V
DD
C1
St/GT
R
P
= (R1R2) / (R1 + R2)
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
R1
ESt
R2
a) decreasing tGTP; (tGTP < tGTA)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
V
DD
C1
St/GT
t
GTA
= (R
p
C1) In (V
DD
/V
TSt
)
R
P
= (R1R2) / (R1 + R2)
R1
ESt
R2
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
4-94
MITEL [ MITEL NETWORKS CORPORATION ]
