MT8920B
CMOS
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Channel Address Register 1 =
Interrupt Modes and Servicing
Static Interrupt Mode
A static interrupt is caused when an incoming byte
matches a predefined byte. The incoming byte from
a selected channel is stored in Interrupt Image
Register (1/2) where it is compared with the contents
of the corresponding Match Byte Register. The
result of the comparison of individual bits is masked
by the contents of the Mask Register (1/2) before it
is used to generate an IRQ. After a static interrupt
occurs, information in the Interrupt Image Register is
frozen until the
µP
performs a read operation on this
register.
When servicing static interrupts assertion of IACK
will cause the contents of the Vector Register, with
the IRQ1 or IRQ2 bit set, to be output on the data
bus. The service routine can subsequently clear IRQ
by reading the Interrupt Image Register.
Alternatively, the IRQRST bit in Control Register 1
can be set to clear the associated interrupt registers.
Static Interrupts are selected using IRQ1MODE and
IRQ2MODE bits in Control Register 1. Interrupts are
then enabled to the IRQ pin with IRQ1EN and
IRQ2EN bits of the same register.
Dynamic Interrupt Mode
A dynamic interrupt is generated by a change of
state of bits in a selected channel. A 0 to 1 transition
or a 1 to 0 transition or a simple change of state from
the previous state (toggle) can be detected. The
type of transition to be detected is selected using two
bits, one from the Match Byte Register (1/2) and one
from the Interrupt Mask Register (1/2), in the
corresponding bit positions. Table 5 shows how the
two registers are programmed.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
(channel 4 of STi0 selected)
Match Byte Register 1 =
Interrupt Mask Register 1 =
(When bit D
3
toggles 0 to 1)
Dynamic interrupts from interrupt path 1 would then
be enabled using the Control Register 1.
Control Register 1 =
0
0
0
0
0
1
0
1
This would cause interrupt 1 path to be enabled
while interrupt 2 path is disabled.
As with static interrupts, upon serving a dynamic
interrupt, assertion of IACK will cause the contents
of the Vector Register, with the appropriate path bit
set, to be output on the data bus. The information
contained in the channel is frozen in the Interrupt
Image Register.
To clear a dynamic interrupt,
however, the
µP
must read the Interrupt Flag
Register of the path responsible for the interrupt to
determine which bit caused the interrupt. The bit in
the corresponding position will be set to 1 and
reading this register will clear its contents.
Alternatively, as with static interrupts, the IRQRST bit
in Control Register 1 can be set to clear the Image
Interrupt Register, Flag Register and path bits in the
Vector Register.
Dynamic Interrupts are selected using IRQ1MODE
and IRQ2MODE bits in Control Register 1 and are
enabled using IRQ1EN and IRQ2EN in the same
register.
MMS Pin Reset
The STPA can be RESET in Mode 1 using the MMS
pin (27). Applying a low pulse (0V) to MMS after
power is applied to the device will reset all control
and interrupt registers to 00
16
.
This can be
accomplished on power up with a simple R-C circuit
as shown in Figure 8.
V
DD
Match
Byte
Register
bit D
X
0
0
1
1
Mask
Byte
Register
bit D
X
0
1
0
1
Transition Type Detected
on Incoming bit D
X
(x = 0 ....7)
Mask Bit D
X
0 to 1 transition
1 to 0 transition
Toggle
R
STPA
MMS
27
C
Table 5 - Dynamic Interrupt Types
For example, the following steps are required to
generate an interrupt when bit D
3
of channel 4
changes state from 0 to 1 (all other bits are masked):
Figure 8 - MMS Reset Function
3-12
MITEL [ MITEL NETWORKS CORPORATION ]
