CMOS
Control Register 2
Bits D
3
= 0, D
2
= 1
Tx0
Rx0
MT8920B
Control Register 2
Bits D
1
= 0, D
0
= 1
µP
STo0
µP
Rx0
STi0
STo0
STi0
Tx1
a)
Control Register 2
Bits D
3
= 1, D
2
= 0
Tx0
a)
1 Frame Delay
STo1
Control Register 2
Bits D
1
= 1, D
0
= 0
Tx0
µP
Rx0
STo0
STi0
µP
STo0
STi0
STo1
Rx0
Tx1
b)
Control Register 2
Bits D
3
= 1, D
2
= 1
Tx0
Rx0
STi0
Tx1
c)
1 Frame Delay
c)
STo0
STi0
STo1
b)
Control Register 2
Bits D
1
= 1, D
0
= 1
µP
Tx0
µP
Rx0
STo0
Figure 5 - Loopback Configurations
Interrupt Mask Register (1/2):
In static mode the
contents of this register masks bits in the Match Byte
Register that are ’don’t care’ bits
1 - bit masked
0 - bit not masked
In dynamic mode, each bit in this register and the
corresponding bit in the Match Byte Register define
what type of dynamic interrupt is selected. (Refer to
Table 5.)
Interrupt Flag Register (1/2):
In static mode
the least significant bit in this register is set to 1 to
flag the corresponding path in which the interrupt
occurs.
D7
In dynamic mode this register sets the bits which
reflect the position of the bits in the corresponding
Interrupt Register which caused the interrupt.
V
7
Figure 6 - STo1 Configurations
Interrupt Vector Register
This register shown in Figure 7 is common to both
interrupt paths and stores an 8 bit vector number
which will be output on the data bus when
Interrupt Acknowledge (IACK) is asserted. Bits
labelled V
2
- V
7
are stored by the controlling
µP.
Bits IRQ1 and IRQ2 are set by the STPA to indicate
which path caused the interrupt. This creates unique
vectors which are used by the
µP
to vector to
interrupt service routines. This feature may be
bypassed by simply not asserting IACK during
interrupt acknowledged.
D6
V
6
D5
V
5
D4
V
4
D3
V
3
D2
V
2
D1
D0
IRQ2 IRQ1
Figure 7 - Interrupt Vector Registers
3-11
MITEL [ MITEL NETWORKS CORPORATION ]
