MT8941 CMOS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
ENVC
MS0
C12i
MS1
F0i
VDD
RST
CV
CVb
Yo
•
NC
CVb
Yo
Bi
Ai
MS3
ENC2o
5
25
24
23
22
21
20
19
NC
MS1
6
F0i
7
F0b
Bi
Ai
8
F0b
MS2
C16i
MS2
C16i
ENC4o
C8Kb
C4o
9
MS3
ENC2o
C2o
C2o
C4b
10
11
ENC4o
VSS
24 PIN PDIP
28 PIN PLCC
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
DIP PLCC
1
1
EN
Variable clock enable (TTL compatible input) - This input directly controls the three states
of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts
it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1
is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.
CV
2
2
MS0 Mode select ‘0’ input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
3
4
3
6
C12i 12.352 MHz Clock input (TTL compatible) - Master clock input for DPLL #1.
MS1 Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
5
6
7
8
F0i
Frame pulse input (TTL compatible) - This is the frame pulse input at 8 kHz. DPLL #1
locks to the falling edge of this input to generate T1 (1.544 MHz) clock.
F0b Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as
an input to an external frame pulse.
7
9
MS2 Mode select-2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
8
9
10
C16i 16.384 MHz Clock input (TTL compatible) - Master clock input for DPLL #2.
11 EN
Enable 4.096 MHz clock (TTL compatible input) - This active high input enables C4o (pin
C4o
11) output. When LOW, the output C4o is in high impedance condition.
10
12
C8Kb Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) - This is the 8
kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode.
When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal
provided by DPLL #1 which is also connected internally to DPLL #2.
11
13
14
C4o Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
12
V
Ground (0 Volt)
SS
3-44
MITEL [ MITEL NETWORKS CORPORATION ]
