MT8960/61/62/63/64/65/66/67
Functional Description
Figure 1 shows the functional block diagram of the
MT8960-67. These devices provide the conversion
interface between the voiceband analog signals of a
telephone subscriber loop and the digital signals
required in a digital PCM (pulse code modulation)
switching system. Analog (voiceband) signals in the
transmit path enter the chip at V
X
, are sampled at
8kHz, and the samples quantized and assigned 8-bit
digital values defined by logarithmic PCM encoding
laws. Analog signals in the receive path leave the
chip at V
R
after reconstruction from digital 8-bit
words.
Separate switched capacitor filter sections are used
for bandlimiting prior to digital encoding in the
transmit path and after digital decoding in the receive
path. All filter clocks are derived from the 2.048 MHz
master clock input, C2i. Chip size is minimized by
the use of common circuitry performing the A to D
and D to A conversion. A successive approximation
technique is used with capacitor arrays to define the
16 steps and 8 chords in the signal conversion
process. Eight-bit PCM encoded digital data enters
and leaves the chip serially on DSTi and DSTo pins,
respectively.
ISO
2
-CMOS
are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and
above.
The filter output signal is an 8 kHz staircase
waveform which is fed into the codec capacitor array,
or alternatively, into an external capacitive load of
250 pF when the chip is in the test mode. The digital
encoder generates an eight-bit digital word
representation of the 8 kHz sampled analog signal.
The first bit of serial data stream is bit 7 (MSB) and
represents the sign of the analog signal. Bits 4-6
represent the chord which contains the analog
sample value. Bits 0-3 represent the step value of
the analog sample within the selected chord. The
MT8960-63 provide a sign plus magnitude PCM
output code format. The MT8964/66 PCM output
code conforms to the AT &T D3 specification, i.e.,
true sign bit and inverted magnitude bits. The
MT8965/67 PCM output code conforms to the CCITT
specifications with alternate digit inversion (even bits
inverted). See Figs. 3 and 4 for the digital output
code corresponding to the analog voltage, V
IN
, at V
X
input.
The eight-bit digital word is output at DSTo at a
nominal rate of 2.048 MHz, via the output buffer as
the first 8-bits of the 125 µs sampling frame.
Transmit Path
Analog signals at the input (Vx) are firstly
bandlimited to 508 kHz by an RC lowpass filter
section. This performs the necessary anti-aliasing
for the following first-order sampled data lowpass
pre-filter which is clocked at 512 kHz. This further
bandlimits the signal to 124 kHz before a fifth-order
elliptic lowpass filter, clocked at 128 kHz, provides
the 3.4 kHz bandwidth required by the encoder
section. A 50/60 Hz third-order highpass notch filter
clocked at 8 kHz completes the transmit filter path.
Accumulated DC offset is cancelled in this last
section by a switched-capacitor auto-zero loop which
integrates the sign bit of the encoded PCM word, fed
back from the codec and injects this voltage level
into the non-inverting input of the comparator. An
integrating capacitor (of value between 0.1 and 1 µF)
must be externally connected from this point (ANUL)
to the Analog Ground (GNDA).
The absolute gain of the transmit filter (nominally 0
dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1
dB steps by means of three binary controlled gain
pads.
The resulting bandpass characteristics with the limits
shown in Figure 10 meet the CCITT and AT&T
recommended specifications. Typical atttenuations
6-22
Receive Path
An eight-bit PCM encoded digital word is received on
DSTi input once during the 125 µs period and is
loaded into the input register. A charge proportional
to the received PCM word appears on the capacitor
array and an 8 kHz sample and hold circuit
integrates this charge and holds it for the rest of the
sampling period.
The receive (D/A) filter provides interpolation filtering
on the 8 kHz sample and hold signal from the codec.
The filter consists of a 3.4 kHz lowpass fifth-order
elliptic section clocked at 128 kHz and performs
bandlimiting and smoothing of the 8 kHz "staircase"
waveform. In addition, sinx/x gain correction is
applied to the signal to compensate for the
attenuation of higher frequencies caused by the
capacitive sample and hold circuit. The absolute
gain of the receive filter can be adjusted from 0 dB to
-7 dB in 1 dB steps by means of three binary
controlled gain pads.
The resulting lowpass
characteristics, with the limits shown in Figure 11,
meet the CCITT and AT & T recommended
specifications.
Typical attenuation at 4.6 kHz and above is 30 dB.
The filter is followed by a buffer amplifier which
will drive 5V peak/peak into a 10k ohm load, suitable
for driving electronic 2-4 wire circuits.
MITEL [ MITEL NETWORKS CORPORATION ]
