ISO-CMOS
AC Electrical Characteristics
†
- Clock Timing (Figures 12 and 13)
Characteristics
1
2
3
4
5
6
7
I
N
P
U
T
S
Clock Period*
Clock Width High
Clock Width Low
Clock Transition Time
Frame Pulse SetupTime
Frame Pulse Hold Time
Frame Pulse Width
Sym
t
CLK
t
CH
t
CL
t
CTT
t
FPS
t
FPH
t
FPW
20
0.020
244
Min
220
95
110
Typ
‡
244
122
122
20
200
50
Max
300
150
150
Units
ns
ns
ns
ns
ns
µs
ns
MT8981D
Test Conditions
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB:
Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 12 - Frame Alignment
t
CLK
t
CL
2.0V
C4i
0.8V
t
CHL
t
FPH
2.0V
F0i
0.8V
t
FPW
t
FPS
t
CTT
t
FPH
t
FPS
t
CTT
t
CH
Figure 13 - Clock Timing
2-27
MITEL [ MITEL NETWORKS CORPORATION ]
