MT90210
Frame Boundary Established by F0i
Preliminary Information
SCLK
(4 MHz)
SCLK
(8 MHz)
SCLK, C16
(16 MHz)
F0i
Serial I/O
2 Mb/s
Ch. 31, Bit 1
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
Serial I/O
4 Mb/s
Ch. 63, Bit 2
Ch. 63, Bit 1
Ch. 63, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
Ch. 0, Bit 5
Serial I/O
8 Mb/s
Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 0,
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Ch. 0,
Bit 6
Ch. 0,
Bit 5
Ch. 0,
Bit 4
Ch. 0,
Bit 3
Ch. 0,
Bit 2
Figure 6 - Serial Port Functional Timing
last write address
of frame n
W
R
I
T
E
A0-A12
address x
inactive
P0-P7
Data
Out
Data
Out
inactive
WBC
MT90210 finishes writing
data from frame n.
MT90210 will handle parallel por
t
transactions related to frame n +1.
last read address
of frame n
R
E
A
D
A0-A12
address y
inactive
P0-P7
Data
In
Data
In
inactive
WBC
MT90210 finishes reading
data from frame n.
MT90210 will handle parallel port
transactions related to frame n +1.
Figure 7a - WBC and RBC Output Transition
2-152
MITEL [ MITEL NETWORKS CORPORATION ]
