Preliminary Information
Pin Description
Pin #
Name
PLCC LQFP
1
2
3
4
5
51
52
53
54
55
OSC1
OSC2
V
SS4
V
DD4
CSTo
Description
MT9076
Oscillator (3V Input).
This pin is either connected via a 20.000 MHz crystal to OSC2
where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is employed.
Oscillator (3V Output).
Connect a 20.0 MHz crystal between OSC1 and OSC2. Not
suitable for driving other devices.
Negative Power Supply .
Digital ground.
Positive Power Supply .
Digital supply (+3.3V
±
5%).
Control ST-BUS (5V tolerant Output).
CSTo carries serial streams for CAS and CCS
respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive
signaling nibbles (ABCDZZZZ or ZZZZABCD). The most significant nibbles of each ST-
BUS time slot are valid and the least significant nibbles of each ST-BUS time slot are
tristated when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the
position of the valid and tristated nibbles are reversed.
Control ST-BUS (5V tolerant Input).
CSTi carries serial streams for CAS and CCS
respectively a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit
signaling nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this
pin has no function. The most significant nibbles of each ST-BUS time slot are valid and
the least significant nibbles of each ST-BUS time slot are ignored when control bit MSN
(page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid and
ignored nibbles is reversed.
Data ST-BUS (5V tolerant Output).
A 2.048 Mbit/s serial stream which contains the
24/30 PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.
Data ST-BUS (5V tolerant Input).
A 2.048 Mbit/s serial stream which contains the
24/30 (T1/E1) PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)
line.
Data/Read Strobe (5V tolerant Input).
In Motorola mode (DS), this input is the active low data strobe of the processor
interface. In Intel mode (RD), this input is the active low read strobe of the processor
interface.
Chip Select (5V tolerant Input).
This active low input enables the non-multiplexed
parallel microprocessor interface of the MT9076. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
RESET (5V tolerant Input).
This active low input puts the MT9076 in a reset condition.
RESET should be set to high for normal operation. The MT9076 should be reset after
power-up. The RESET pin must be held low for a minimum of 1µsec. to reset the device
properly.
Interrupt Request (5V tolerant Output).
A low on this output pin indicates that an
interrupt request is presented. IRQ is an open drain output that should be connected to
V
DD
through a pull-up resistor. An active low CS signal is not required for this pin to
function.
Data 0 to Data 3 (5V tolerant Three-state I/O).
These signals combined with D4-D7
form the bidirectional data bus of the parallel processor interface (D0 is the least
significant bit).
Negative Power Supply.
Digital ground.
Internal Connection (3V Input).
Tie to V
SS
(Ground) for normal operation.
6
56
CSTi
7
8
57
58
DSTo
DSTi
9
59
DS/RD
10
63
CS
11
64
RESET
12
65
IRQ
13 - 66-69
16
17
18
70
71
D0 - D3
VSS5
IC4
3
MITEL [ MITEL NETWORKS CORPORATION ]
