Preliminary Information
Pin Description (continued)
Pin #
Name
PLCC LQFP
42
17
RxMF/
TxFP
Description
MT9076
Receive Multiframe Boundary / Transmit Frame Boundary (5V tolerant Output).
If
the control bit Tx8KEN (page 02H address 10H bit 2) is low, this negative output pulse
delimits the received multiframe boundary. The next frame output on the data stream
(DSTo) is basic frame zero on the T1 or PCM 30 link. In E1 mode this receive
multiframe signal can be related to either the receive CRC multiframe (page 01H,
address 17H, bit 6, MFSEL=1) or the receive signaling multiframe (MFSEL=0). If the
control bit Tx8KEN is set high, this positive output pulse delimits the frame boundary
(the first bit transmit in the frame) for the digital output stream on pins TXA and TXB.
Bus/Line Syncronization Mode Selection (5V tolerant Input).
If high, C4b and F0b
will be inputs; if low, C4b and F0b will be outputs.
2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (5V tolerant
Output).
The clock extracted from the received signal and used internally to clock in
data received on RTIP and RRING.
4.096 MHz System Clock (5V tolerant Input/Output).
C4b is the clock for the ST-BUS
sections and transmit serial PCM data of the MT9076. In the free-run (S/FR/Exclki=0) or
line synchronous mode (S/FR/Exclki=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR/Exclki=1 and BS/LS=1) this signal is an input clock.
Frame Pulse (5V tolerant Input/Output).
This is the ST-BUS frame synchronization
signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the
PCM30 link. In the free-run (S/FR/Exclki=0) or line synchronous mode (S/FR/Exclki=1
and BS/LS=0) this signal is an output, while in bus synchronous mode (S/FR/Exclki=1
and BS/LS=1) this signal is an input.
Receive Frame Pulse/Receive CCS Clock (5V tolerant Output).
An 8kHz pulse
signal, which is low for one extracted clock period. This signal is synchronized to the
receive DS1 or PCM 30 basic frame boundary.
Internal Connection.
Must be left open for normal operation.
Negative Power Supply.
Digital ground.
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Transmit Analog Power Supply.
Analog supply for the LIU transmitter (+3.3V
±5%).
Transmit TIP and RING(Output).
Differential outputs for the transmit line signal - must
be transformer coupled (See Figure 6).
Transmit Analog Ground .
Analog ground for the LIU transmitter.
IEEE 1149.1a Test Data Input (3V Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Test Data Output (5V tolerant Output).
If not used, this pin should be
left unconnected.
IEEE 1149.1a Test Mode Selection (3V Input).
If not used, this pin should be pulled
high.
IEEE 1149.1a Test Clock Signal (3V Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Reset Signal (3V Input).
If not used, this pin should be held low.
Transmit All Ones (Input).
High - TTIP, TRING will transmit data normally. Low - TTIP,
TRING will transmit an all ones signal.
43
44
18
22
BS/LS
Exclk
45
23
C4b
46
24
F0b
47
25
RxFP
48
49
50
51
52
53
54
55
56
57
58
59
60
26
27
28
29
30
31
32
33
34
35
36
37
38
IC1
V
SS2
V
DD2
VDD
ATx
TTIP
TRING
GND
ATx
Tdi
Tdo
Tms
Tclk
Trst
TxAO
5
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