CMOS
MT9085
512 C4 Cycles
C4
F0
S0-S31
2/4S = 0
S0-S15
2/4S = 1
0
0
1
31
0
1
2
3
63
0
Figure 3 - Serial Input/Output Functional Timing
Frame Boundary Established by F0i
C16i
C4o
C2o
F0o
Serial I/O
2 Mbit/s
Serial I/O
4 Mbit/S
Ch. 31 Bit 1
Ch. 31 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 63 Bit 2
Ch. 63 Bit 1
Ch. 63 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 0 Bit 5
Figure 4 - Channel and Frame Alignment (CKD = 0)
Frame Boundary Established by F0i
C16i
C4o
C2o
F0o
Serial I/O
2 Mbit/s
Serial I/O
4 Mbit/S
Ch. 31 Bit 1
Ch. 31 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 63 Bit 2
Ch. 63 Bit 1
Ch. 63 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 0 Bit 5
Figure 5 - Channel and Frame Alignment (CKD = 1)
2-129
MITEL [ MITEL NETWORKS CORPORATION ]
