MT9126
A
A
A
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A
A
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A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
7 6 5 4 3 2
A
A
A
A
B1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
7 6 5 4 3 2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B3
A
A
A
A
7 6 5 4 3 2
A
A
A
A
A
A
A
A
A
AA
A
AA
A
A
1 2 3 4
AA
x x
AA
A
AA
A
AA
A
AA
A
B1
AA
A
AA
A
AA
A
A
A
A
A
A
A
A
A
1 2 3 4 1 2
A
A
A
A
A
A
A
A
AA
A
AA
AA
A
A
AA
B3
A
AA
A
AA
A
AA
A
A
1 2 3 4
AA
x x
AA
A
AA
A
AA
A
A
A
A
AA
A
A
AA
A
A
1 2
AA
x x x
AA
x
A
AA
A
AA
A
AA
A
B1
AA
A
AA
A
AA
A
AA
A
A
A
SEL = 0
A
A
A
A
A
1 2 1 2 1 2
A
A
A
A
B1 B2 B3
A
A
A
A
AA
A
AA
A
A
B3
AA
AA
A
AA
A
AA
A
AA
A
A
1 2
AA
x x x
AA
x
A
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
1 0 7 6 5 4 3 2 1 0
AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
SEL = 0
AA
AA
AA
AA
AA
AA
1 0 7 6 5 4 3 2 1 0
AA
AA
AA
AA
AA
AA
AA
AA
SEL = 1
AA
AA
AA
AA
AA
AA
AA
B4
AA
AA
AA
1 0 7 6 5 4 3 2 1 0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x x x
AA
AA
x x 1 2 3 4
AA
AA
AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
3 4 1 2 3 4 1 2 3 4
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B4
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2 3 4
AA
x x x x
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2
AA
x x x x x x
AA
AA
AA
AA
AA
AA
AA
AA
B2
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
SEL = 1
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
2 1 2 1 2 1 2
AA
AA
1 2
AA
1
AA
AA
AA
AA
AA
B4
AA
B1 B2 B3 B4
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B4
AA
AA
AA
AA
AA
AA
AA
AA
AA
x x 1 2
AA
x x x x x
AA
x
AA
AA
AA
AA
Preliminary Information
BCLK
ENB1
ENB2/F0od
PCMi/o1
ADPCMo/i
SSI PCM
Bypass
PCMi/o2
PCMi/o1
32 kb/s using bits 1 2 3 4
24 kb/s where bit 4 = x
ADPCMo/i
PCMi/o2
SSI ADPCM
Bypass
PCMi/o1
ADPCM o/i
16 kb/s
PCMi/o2
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 6 - SSI PCM and ADPCM Bypass Relative Timing
8-42
MITEL [ MITEL NETWORKS CORPORATION ]
