MT9126
Preliminary Information
MCLK (C4i)
F0i
C2o
EN1 (output)
F0od/ENB2
PCMi/o1
PCMi/o2
ADPCMi/o
(32/24 kb/s)
bit 4 = x at 24 kbit/s
ADPCMi/o
(16 kb/s)
AA
A
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AAA
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SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
A
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
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AA
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AA
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A
A AAAAAAAAAAAAAAAA A
AA
AAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
A
AAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
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A
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AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
B1
B2
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
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A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
A
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
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AA
A
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A AAAAAAAAAAAAAAAAAAAA
A
AAAA
AA AAAAAAAAAAAAAAAAAAAA
A
A
A
A
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
A
A
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
B3
B4
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
A
AAAA
AA
A
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1234 1234 1234 1234
A
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AAAA
AA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A
A
AA AAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AA
A
B1 B2 B3 B4
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AA AAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AA AAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
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12 12 12 12 12 12 12 12
A
AA AAAAAAAAAAAAAAAAAA
A
A
A
AAAA
AA AAAAAAAAAAAAAAAAAA
A
A
A
AA AAAAAAAAAAAAAAAAAA
B B B B B B B B
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
A
A
AA AAAAAAAAAAAAAAAAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
A
A
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AAAA
A
1 2 3 4 1 2 3 4
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
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SEL = 0
AA
SEL = 1
A
SEL operated for
AA
A
AA
A
AA
16kb/s only
A
A
AAAAAAAAAAAA
AAAAAAAAAAAA
outputs = High impedance
AAAAAAAAAAAA
AAAAAAAAAAAA
inputs = don’t care
AAAAAAAAAAAA
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Note: D &C channels not supported in this mode.
Figure 8 - ST-BUS 16-bit Linear PCM Relative Timing
8-44
MITEL [ MITEL NETWORKS CORPORATION ]
