MT91L60/61
Advance Information
Control Register 2
ADDRESS = 04h WRITE/READ VERIFY
Power Reset Value
0000 0010
Smag/
ITU-T
CSL1 CSL0
CEn
7
DEn
6
D8
5
CSL2
2
A/µ
4
3
1
0
CEn
DEn
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When
low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel
register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation
and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0
on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is
completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of
the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation.
D8
When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default).
A/µ
When high, A-Law encoding/decoding is selected for the MT91L60/61. When low, µ-Law encoding/decoding is
selected.
Smag/ITU-T
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code
assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate
digit inversion (A-Law).
CSL
CSL
CSL
0
Bit Clock rate (kHz)
CLOCKin (kHz)
Mode
2
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
1
0
1
N/A
128
4096
4096
4096
512
ST-BUS
SSI
256
SSI
512
SSI
1536
2048
4096
1536
2048
4096
SSI
SSI (default)
SSI
Note: Bits marked "-" are reserved bits and should be written with logic "0"
16
MITEL [ MITEL NETWORKS CORPORATION ]
