SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
PRE -
CHARGING
/CS
H
L
L
L
L
L
L
L
ROW
ACTIVATING
H
L
L
L
L
L
L
L
WRITE RE-
COVERING
H
L
L
L
L
L
L
L
/RAS
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
/CAS
X
H
H
L
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
H
H
L
L
/WE
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
X
X
X
BA, CA, A8
BA, RA
BA, A8
X
Op-Code,
Mode-Add
X
X
X
BA, CA, A8
BA, RA
BA, A8
X
Op-Code,
Mode-Add
X
X
X
BA, CA, A8
BA, RA
BA, A8
X
Op-Code,
Mode-Add
Address
Command
DESEL
NOP
TBST
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
ILLEGAL*2
NOP*4 (Idle after tRP)
ILLEGAL
ILLEGAL
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT
PRE / PREA
REFA
MRS
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
MITSUBISHI ELECTRIC
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